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CDMA IF VGAs and I/Q Demodulators
with VCO and Synthesizer
MSB
LSB
DATA
*SB
*START BIT MUST BE LOGIC HIGH.
CLK
RISE AND FALL REQUIRED PRIOR TO EN GOING LOW.
EN
Figure 6. 3-Wire Interface Timing Diagram
Table 4. Control Register, Default State: 0B57 h, Address: 110 b
POWER-
BIT
BIT ID
BIT NAME
UP
LOCATION
FUNCTION
STATE
0 = LSB
TM
TEST_MODE
0
12
Must be 0 for normal operation.
Logic “1” causes the charge-pump output CP_OUT to source cur-
rent when f REF /R > f VCO /M. This state is used when the VCO tune
POL
CP_POL
1
11
polarity is such that increasing voltage produces increasing fre-
quency. Logic “0” causes CP_OUT to source current when f VCO /M
> f REF /R. This state is used when increasing tune voltage causes
the VCO frequency to decrease.
TE
TC
DS
VB
VS
BD
BE
FT
IS
TEST_ENABLE
TURBO_CHARGE
DIV_SEL
VCO_BYP
VCO_SEL
BUF_DIV
BUFEN
FM_TYPE
IN_SEL
0
1
1
0
1
0
1
0
1
10
9
8
7
6
5
4
3
2
Must be 0 for normal operation.
Logic “1” activates turbocharge mode, which provides rapid fre-
quency acquisition in the PLL.
Logic “1” selects M1/R1 divide ratios. Logic “0” selects M2/R2.
Logic “1” bypasses the VCO inputs for external VCO operation.
Logic “1” selects VCO_H. Logic “0” selects VCO_L.
Logic “1” selects divide-by-2 on LOOUT port. Logic “0” bypasses
divider.
Logic “1” disables LOOUT. Logic “0” enables LOOUT.
Active in FM mode. Logic “0” selects quadrature demodulator for
FM mode. Logic “1” selects downconversion to I port.
Logic “0” selects FM input port. Logic “1” selects CDMA input.
Logic “0” enables standby mode, which shuts down the VGA and
SB
STBY
1
1
demodulator stages, leaving the VCO locked and the registers
active.
SD
SHDN
1
0
Logic “0” enables register-based shutdown. This mode shuts down
everything except the M and R latches and the serial bus.
16
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